IRS2500SPBF【PDF 13/22 页】IC PFC

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Sheet目录38

9页 10页 11页 12页 [13页]14页 15页 16页 17页

IRS2500S

www.irf.com

?2012 International Rectifier

level and the discharge time will be longer giving a

lower switching frequency.

The PFC control circuit of the IRS2500 (Figure

10) includes six control pins: VBUS, COMP, ZX,

OUT, VDC and OC. The VBUS pin measures the

DC bus voltage through an external resistor voltage

divider. The COMP pin voltage determines the on-

time of MPFC and sets the feedback loop response

speed with an external RC integrator. The ZX pin

detects when the inductor current discharges to

zero each switching cycle using a secondary

winding from the PFC inductor. The OUT pin is the

low-side gate driver output for the external

MOSFET, MPFC. The VDC pin senses the line

input cycle providing phase information to control

the on time modulation described in the next

section. The OC pin senses the current flowing

through MPFC and performs cycle-by-cycle over-

current protection.

RVBUS1

RVBUS2

RVBUS

CCOMP

LPFC

MPFC

RPFC

DFPC

CBUS

(+)

(-)

RZX

PFC

Control

VBUS

COMP

OUT

COM

ROC

RDC

RIN

VDC

Figure 10: IRS2500 simplified PFC control

circuit.

The VBUS pin is compared with a fixed internal

2.5V reference voltage for regulating the DC output

voltage (Figure 11). The feedback loop error

amplifier increases or decreases the COMP pin

voltage. The resulting voltage on the COMP pin

sets the threshold for the charging of the internal

timing capacitor (C1, Figure 11) and therefore

determines the on-time of MPFC.

The error amplifier operates at a slow loop speed

preventing rapid changes in PWM duty cycle during

a single input line cycle. This prevents distortion

achieving high power factor and low THD.

R Q

2.0V

VBUS

COMP

5.1V

2.5V

2.75

OUT

R2 Q

COMP3

COMP4

COMP5

RS3

RS4

VCC

WATCH

DOG

TIMER

1.2V

On Time

Modulator

VDC

Figure 11: IRS2500 detailed PFC control circuit.

The off-time of MPFC is determined by the time it

takes the LPFC current to discharge to zero. The

zero current level is detected by a secondary

winding on LPFC that is connected to the ZX pin

through an external current limiting resistor RZX. A

positive-going edge exceeding the internal

threshold VZX+ signals the beginning of the off-

time. A negative-going edge on the ZX pin falling

below VZX- will occur when the LPFC current

discharges to zero, which signals the end of the off-

time and MPFC is turned on again (Figure 12). The

ZX pin is internally biased to ensure that the voltage

detected from the inductor drops fully to zero before

triggering the next PWM cycle. A wide hysteresis

prevents false triggering by ringing oscillations.

The cycle repeats itself indefinitely until the

IRS2500 is disabled through an over-voltage

condition on the DC bus or if the negative transition

of ZX pin voltage does not occur. Should the

negative edge on the ZX pin not occur, MPFC will

remain off until the watch-dog timer forces a turn-on

of MPFC for an on-time duration programmed by

the voltage on the COMP pin. The watch-dog

pulses occur every 300-400us (tWD) indefinitely

until a correct positive and negative-going signal is

detected at the ZX pin and normal operation is

resumed. Should the OC pin voltage exceed the

VOCTH over-current threshold during the on-time

the gate drive output will turn off. The circuit will

then wait for a negative-going transition on the ZX

pin or a forced turn-on from the watch-dog timer to

turn the output on again.

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